1. Field of the Invention
The present invention relates to integrated circuits. In particular, the present invention is an integrable power up reset pulse generator for producing a reset pulse to logic elements of a FET integrated circuit when power is initially applied to the integrated circuit.
2. Description of the Prior Art
In digital integrated circuits, it is sometimes desirable to initialize the circuit to a known state when power is first applied to the integrated circuit (i.e. "power up"). This ensures proper initialization of the operating state of the logic elements of the circuit, and also simplifies test procedures. By starting the logic elements of the circuit in a known state, a predetermined set of electrical instructions can be used so that the circuit reaches the desired operating condition.
In the past, various capacitor and transistor time constant circuits have been used to generate a reset pulse upon power up. This reset pulse is applied to the appropriate logic elements to initialize the integrated circuit in a known state.
With CMOS integrated circuits, low power consumption is an important feature. To be useful in conjunction with the CMOS integrated circuit, a power up reset pulse generator circuit must consume very little power both during initial power up, and particularly after the power is reached its static state.